1. Field of the Invention
The present invention relates to decoupling gate to contact and gate to metal capacitances from overall gate capacitance, and particularly to a method to extract gate to source/drain and overlap capacitances and a test key structure used for the method.
2. Description of the Prior Art
In the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. Accordingly, smaller feature sizes, smaller separations between features and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher cost efficiency in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
As device sizes continue to shrink, however, parasitic capacitance effects may become noticeable and/or problematic. There are a number of parasitic capacitances associated with a MOS transistor. For example, ion implantation is utilized to create the source and drain extension regions (LDD regions) in the transistor. A high temperature anneal is subsequently employed to activate the implanted dopants, and some of the dopants can migrate toward gate channel due to lateral diffusion.
The overlap regions in which LDD regions overlap with gate structure can give rise to “overlap capacitances” since the gate structure includes at least a conductive layer overlying at least a dielectric material over a substrate, and the at least a dielectric material, in turn is situated between the gate structure and the diffused conductive dopants in the substrate. The value of the overlap capacitance depends upon the area or degree of overlap between the gate structure and the diffused dopants, among other things. As the size of the gate structure is reduced, the overlap capacitance becomes significant to reduce transistor and IC performance. Accordingly, many test methods are developed for trying to obtain the value of the overlap capacitance. However, as the IC scale is down to 0.13 or 0.09 μm or even beyond that, contact to gate or metal layer to gate capacitances will affect the accuracy of overlap and gate to source/drain capacitances. A cross-sectional view of a conventional MOS transistor is shown in FIG. 1. The MOS transistor 1 includes a gate 3 formed over a semiconductor substrate 2, a gate dielectric layer 4 formed between the semiconductor substrate 2 and the gate 3, composite spacers composed of spacers 5a and 5b formed on both sidewalls of the gate 3, a pair of source/drain 6 formed in the semiconductor substrate on two opposite sides of the gate 3, a pair of source/drain extensions 7 extending under the gate 3 to overlap with the gate 3, a salicide layer 8 on each source/drain 6, a contact 9 formed on each salicide layer 8, and a metal layer 10 formed on the contacts 9. Capacitances exist between the gate and the source/drain (C2), the source/drain extension (C1), the contact (C3), and the metal layer (C4). C1 is overlap capacitance but can not be decoupled from C2 during measurement.
Currently, a TCAD simulation method is employed to predict the capacitance with or without C3 and C4; however the real data is not known.
Conventional test keys are used for attempt on measuring the overlap capacitance; nevertheless, the four items: C1, C2, C3, and C4 are measured inseparably. What usually concerned are C1 and C2, and C3 and C4 are usually neglected. However, as the technology node shrinks down, C3 and C4 become too higher to be neglected. FIG. 10 is a diagram showing a plot of C1+C2+C3+C4 capacitance versus gate-to-source voltage in a conventional test key with a channel width of 10 μm and a channel length of 1.2 μm, wherein C2, C3 and C4 are not functions of VGS, i.e. C2, C3 and C4 do not change along with VGS, and therefore C1 contributes to the total capacitance change along with VGS.
Accordingly, it is a need for developing a novel method to extract C1+C2 capacitances and a test key structure for the method, to obtain the pure C1+C2 capacitances.